Introduction
In the hierarchy of computer storage systems, high speed small capacity memory between the central processor and main memory. It constitutes a level one memory together with the main memory. The scheduling and transfer of information between the cache and the main memory is automated by the hardware, and the programmer does not feel the presence of the cache, so it is transparent to the programmer. The role of the cache memory In the development of computer technology, the main memory access speed has been much slower than the central processor operation speed, so that the high-speed processing capability of the central processing unit cannot be fully utilized, and the working efficiency of the entire computer system is affected.
In the hierarchy of computer storage systems, high speed small capacity memory between the central processor and main memory. It constitutes a level one memory together with the main memory. The scheduling and transfer of information between the cache and the main memory is automated by the hardware, and the programmer does not feel the presence of the cache, so it is transparent to the programmer.
Article Core
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Cache memory
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Purpose
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Introduce the function, structure and working principle of cache memory.
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Application
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Semiconductor industry.
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Keywords
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Cache memory
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Catalog
Introduction
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Principle of CACHE Implementation
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Key Indicators for Evaluating CACHE Performance
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Basic Operation Principle of CACHE
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1. Composition of CACHE Storage Unit
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2. The Principle of Cache Memory
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Three Image Modes of CACHE
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1.Full-associative Mapping
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2. Direct Mapping
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3. Multiplex (two-way) Group Connection Mode
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The Role of Cache Memory
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Several Problems In the Practical Use of CACHE Memory
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Read Hit Rate
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Principle of CACHE Implementation
Copy a small amount of information (data or instructions) most likely to be used by the CPU from main memory to CACHE. When the CPU uses this information again, it does not have to access the slow main memory, but directly from the fast CACHE. Get it, which increases the speed.
Key Indicators for Evaluating CACHE Performance
To have a high enough hit rate, when the CPU needs to use the data in the main memory, in most cases, it can be obtained directly from CACHE, and read the main memory as little as possible. Said the ratio of the two is the hit rate.
Basic Operation Principle of CACHE
1. Composition of CACHE Storage Unit
The storage unit of CACHE is composed of three parts.
1 valid bit: "0" means the unit is not used yet, "1" means the data is valid.
(1) The CACHE unit does not necessarily correspond to the main memory implementation in word units, because storing a complete main memory address occupies too many bits.
(2) When CACHE exchanges information with the main memory, it is not always exchanged in units of one main memory word. The data transfer is usually performed in the form of a cache line size.
2. The Principle of Cache Memory
The cache memory typically consists of a high speed memory, associative memory, replacement logic circuitry, and corresponding control circuitry. In a computer system with a cache, the address of the central processor accessing the main memory is divided into three fields: a row number, a column number, and an intra-group address. Thus, the main memory is logically divided into rows; each row is divided into a number of memory cell groups; each group contains several or tens of words. The high speed memory is also divided into rows and columns of memory cell groups accordingly. The number of columns is the same, the size of the group is the same, but the number of lines in the high-speed memory is much less than the number of lines in the main memory.
Associative memory is used for address association and has the same number of rows and columns as the high-speed memory. When a certain row of memory cells in a column of the main memory is transferred to an empty memory cell group in the same column of the high speed memory, the memory cell corresponding to the associative memory records the row number of the loaded memory cell group in the main memory.
When the central processor accesses the main memory, the hardware first automatically decodes the column number field of the access address to compare all the row numbers of the column of the associative memory with the row number field of the access main memory address: Similarly, indicating that the main memory unit to be accessed is already in the high speed memory, called a hit, the hardware maps the address of the access main memory to the address of the high speed memory and performs an access operation; if they are different, indicating the unit Not in high-speed memory, called off-target, the hardware will perform access to the main memory operation and automatically transfer the main memory cell group in which the cell is located into the memory cell group in the same column of the high-speed memory, while the group is in the main The line number in the memory is stored in the unit corresponding to the Lenovo memory.
When there is off-target and there is no empty position in the corresponding column of the high-speed memory, a certain group in the column is eliminated to make a free location to store the newly transferred group. This is called replacement. The rule for determining replacement is called the replacement algorithm. Commonly used replacement algorithms are: least recently used (LRU), first in first out (FIFO) and random (RAND). Replacing the logic circuit is to perform this function. In addition, in order to maintain the consistency of the contents of the main memory and the high-speed memory when performing the write main memory operation, the hit and miss target must be processed separately:
(1) When the write operation hits, the write direct method can be used (that is, the main memory and the high speed are simultaneously written) Memory) or writeback (ie, write only to the high speed memory and mark the group modified.
(2) Write allocation method (i.e., write to note memory and transfer the group to high-speed memory) or write-not allocation method (i.e., write only to main memory but not to high-speed memory) can be used when write operation misses target.
The performance of cache is usually measured by hit rate. The factors affecting the hit rate are the capacity of high-speed memory, the size of storage cell group, the number of arrays, the method of address association and comparison, the replacement algorithm, the method of writing operation and the characteristics of program, etc.
Computers using cache technology are quite common. Some computers also use multiple cache memory, such as system cache, instruction cache and address conversion cache, to improve system performance. With the increasing capacity of main memory, the capacity of cache memory is also increasing.
Three Image Modes of CACHE
Address mapping: When copying the data of the main memory address to the cache, the address of the main memory is also processed into a CACHE flag field after being processed by a certain function relationship. This process is called the CACHE address image.
Address translation: When the program is executed, the main memory address is converted to the address of the access CACHE. This process is called CACHE address translation.
The treatment of the two is closely related.
1.Full-associative Mapping
Address image: When writing to CACHE, all the addresses of the main memory should be written to the flag field of CACHE.
Address translation: the entire address of the main memory is read to compare with the flag field of each unit in the CACHE.
Advantages: The hit rate is relatively high, and the Cache storage space utilization is high.
Disadvantages: The comparison address field must be compared with the flag field of each unit in the entire CACHE, so the line is complicated, the cost is too high, and it is difficult to implement, but it is only suitable for CACHE with small capacity.
2. Direct Mapping
Address image: When writing to CACHE, only the main section number is written to the CACHE flag field.
Address translation: To access the intra-segment offset address in the main memory address to access a CACHE unit, simply compare the segment number of the main memory address with the contents of the flag field.
Advantages: The address mapping mode is simple. When data is accessed, it is only necessary to check whether the area numbers are equal, so that a relatively fast access speed can be obtained, and the hardware device is simple.
Disadvantages: frequent replacement operations, low hit rate.
3. Multiplex (two-way) Group Connection Mode
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