Introduction
The rapid development of information technology requires storage technology to provide faster, larger capacity, lower power consumption, smaller size, longer life and higher reliability. At present, the development of storage technology has not kept pace with the development of processors, and has become a bottleneck restricting the development of computing technology. Traditional semiconductor process technology has gradually approached the physical limit, and it is difficult to greatly improve the performance of the memory. If there is a breakthrough, it is necessary to find another way and find new principles and methods. At present, some new storage technologies and corresponding new memories that are being researched and developed for the new century bring a hope for future information storage technologies, some of which have been or are partially implemented in the laboratory. Work towards commercialization goals. For example: Associative Memory Technology and Memory CAM with Addressable Addressing, Intelligent Processing Technology and Smart Memory, Superconducting Technology and Josephson Junction RAM, Holographic Storage Technology and Holographic Memory, Single Electronic Storage Technology and Single Electronic Memory, Proton Preservation Information Technology And proton memory, hydrogen atom storage technology and hydrogen atomic memory, biocircuit technology and protein molecular memory, next-generation information storage technology and high-speed mass storage, building electric field technology and analog memory, optical storage technology and three-dimensional optical memory, nanowires New information storage, etc.
Article Core
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New Memory Technologies
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Purpose
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Introduce what the new memory technologies are and what problems they can solve?
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Application
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Semiconductor Industry.
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Catalog
Introduction
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Ⅰ Overview
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Ⅱ Embedded Memory Problems
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Ⅲ Power Problems in Large Systems
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Ⅳ Why New Memory Can Solve the Problem
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Ⅴ New Memory Type
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5.1 PCM，Phase Change Memory
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5.2 FRAM or FeRAM，Ferroelectric RAM
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5.3 MRAM，Magnetic RAM
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5.4 RRAM or ReRAM，Resistive RAM
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Ⅵ Comparison of New Memory Technologies
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6.1 Selector Type
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6.2 Persistence
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6.3 Scalability
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6.4 Process Complexity
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6.5 Disadvantages
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Ⅶ Conclusion
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Ⅰ Overview
Small memory cell size, high performance, and low power consumption have always been the goal of the memory industry. However, below 14nm, the semiconductor process migrated to Fin-FET, a new transistor structure that could not be directly applied to existing embedded memory components. Furthermore, in order to meet the high computing power requirements of future artificial intelligence and edge computing, high-capacity memories such as DRAM and NAND flash memory have been unable to keep up with the demand.
Therefore, the semiconductor industry is at a turning point. Embedded memory in microcontrollers and ASICs, as well as discrete memory chips for all applications, from handheld mobile devices to supercomputers, are considering replacement. These replacements will help system designers reduce power consumption, extend battery life in handheld mobile devices or reduce data center system cooling requirements, as well as improve system performance to meet future high-performance computing systems. In some cases, replacing traditional memory types can also reduce system cost by using more advanced process technologies or system designs.
Although some new memory technologies have been developed, in this highly competitive market, only a few can succeed. However, no matter which technology wins, these new non-volatile technology systems will certainly consume less power than existing embedded NOR flash and SRAM, or discrete DRAM and NAND flash systems.
Jason Pontin: Can technology solve our big problems?
Ⅱ Embedded Memory Problems
There are two issues, the size of the embedded memory and the power consumption.
Advanced logic processes have surpassed 14nm and migrated to Fin-FET structures, and embedded NOR flash memories used for on-chip storage over the past decade or more have lost the ability to keep up with these processes. This problem is known as the "scaling limit" of flash - no matter how much the rest of the CMOS on the chip can shrink, the flash can't keep up. New embedded memory technologies must be available to match these advanced process ASICs and MCUs.
Embedded NOR flash is not the only one affected by process evolution. Embedded SRAM also faces similar problems. As the process shrinks to tens of nanometers or less, the size of the SRAM memory cell cannot keep up. Unlike NOR flash, the problem with SRAM is that the size of its memory cells does not shrink in proportion to the process. When the process shrinks by 50%, it may only shrink by 25%.
This limits the development of embedded NORs and embedded SRAMs, and we need new storage unit technologies to continue to scale down in proportion to the process. Fortunately, these technologies have existed and have been in development for many years.
Another issue is the strong argument for moving to new memory technologies, which are that memory consumes too much power. IoT and mobile devices operate on battery power, and their memory must be carefully chosen because they consume most of the battery power and reduce battery life, while new embedded memory technologies can reduce power consumption in response to this demand.
The next-generation mobile architecture will introduce higher computing power requirements for artificial intelligence and edge computing, while requiring lower power consumption to meet consumer expectations and win in tough market competition. Of course these must be achieved at low cost, which is the challenge of existing memory technologies. Most of today's battery-powered mobile devices and MCUs used in a variety of other applications are fabricated in a CMOS process, and the CMOS process supports two memory technologies: NOR flash and SRAM. Although these techniques are easily embedded in CMOS logic processes, they typically consume more power than expected.
When larger memories are needed, designers often add external memory chips, such as SPI (Serial Peripheral interface) NOR flash, NAND flash, DRAM, or a combination of these. However, these external memories have a greater impact on power consumption.
The problems with the two existing memories forced designers to begin evaluating new memory technologies in an attempt to solve them completely.
Ⅲ Power Problems in Large Systems
At the other end of the Internet of Things, in the cloud, the data center server's memory and data storage architecture is also important because power consumption is often one of the most costly elements of the data center, especially when it comes to cooling systems.
DRAM and NAND flash are the mainstream storage technologies used today in computing systems, from smartphones to data processing devices. However, for the design of the computing system, these two memory types cannot exist alone, because although the DRAM supports fast reading and writing, the charge of the capacitor of the DRAM memory cell will decay and disappear within a few milliseconds, so it is necessary to constantly Refreshing, while refreshing consumes a lot of power. Even if the system is idle, DRAM needs to be constantly refreshed with power.
Approximately 20% of the power consumed by the 8Gb DRAM chip is used for refresh, accounting for 25 milliwatts of total chip power consumption of 140 milliwatts. If the power is turned off, the contents of the DRAM will disappear (volatile memory) - even if the power is restored, the DRAM is not suitable for use as a boot, application, operating system, etc. code storage. The system must be paired with other nonvolatiles. Sex memory to perform code storage functions.
In addition, DRAM is relatively slow due to its multIplexed addressing technology. DRAM row address selection (RAS) and column row address selection (CAS) allow random reads to take between 25 and 300 nanoseconds (ns), and this extended time results in higher total energy consumption.
Flash Memory stores data that is not attenuated and can retain its content for many years after a power outage, but NOR flash is much more expensive than DRAM, and NAND flash is sequential reads and cannot be accessed to specific bytes. This does not match the need for computer operations to randomly address reads. So NAND flash must be paired with DRAM for code storage use.
Like DRAM, NAND flash also has some features that cause it to consume more power than expected. First, it requires an on-chip charge pump to generate a high internal voltage. Second, the write speed of NAND flash is also very slow. The most troublesome thing is that the NAND flash can't directly overwrite the old data when writing. Before the new data is written to the flash, the original stored data must be erased, and the entire page must be written once (Page, usually 8,096 bytes), it is not possible to write only a single specific byte.
Flash technology does not use the same mechanism to program or erase content. You can't just erase a single bit, byte, or page. Instead, you must pick up the block. The block usually contains Hundreds of thousands of pages. Page writing is a slow and energy-intensive process that typically takes 300 microseconds (μs) and consumes 80 microjoules (compared to 2 microjoules when read). Block erase (requires the high internal voltage mentioned above) takes longer, typically 2 milliseconds (ms), and consumes 150 microjoules of energy. Despite these big drawbacks, NAND flash systems are very cheap, so designers are willing to sacrifice these NAND complex write processes and high energy costs in exchange for their low cost.
Most smartphones and computing systems use a mix of DRAM and NAND flash to meet their memory and storage needs. In smartphones, when the phone is turned on, DRAM saves a copy of the program for execution, while NAND stores programs, photos, videos, music, and other speed-insensitive data when the power is turned off. The compute system server stores programs and data in its DRAM main memory (the server does not power down unless there is a power outage), and an SSD solid state drive (NAND State Drive) using NAND flash is configured for long-term and backup storage.
Smaller systems may use NOR flash instead of NAND flash and SRAM instead of DRAM, provided their memory requirements are very small. The cost per byte of NOR flash is one or two orders of magnitude higher than NAND flash, and the cost of SRAM is orders of magnitude higher than the cost of DRAM.
Ⅳ Why New Memory Can Solve the Problem
The aforementioned power consumption of memory used today has not existed in many of the new memory technologies currently under development. In addition, these new types of memories are non-volatile, so there is no need to refresh them. This automatically reduces power consumption by 20% compared to DRAM. Since they both overwrite old data without erasing, you can save the high erase power required for flash and the delay caused by slow erase cycles (this property is called In-Situ Programming). Compared to flash memory, these new technologies have very low write process energy requirements that reduce or eliminate the need for inefficient charge pumps. Finally, all of these new technologies provide random data access, reducing the need to keep two copies—one in flash and one in DRAM.
Needless to say, whenever any new memory technology is used to replace today's traditional DRAM + NAND flash architecture, all of these attributes will result in significant power savings and performance improvements.
The new types of memory we will introduce include the following.
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